module tb_shiftreg();
    reg load;
    reg [3:0] in;
    reg sin, clk, reset;
    reg shift;
    wire sout;
    wire [3:0] q;
    shiftreg dut(shift, load, in, sin, clk, sout,q, reset);
    always
    begin
        clk = 1; #5; clk = 0; #5;
    end
    initial
    begin
        $dumpfile("tb_shiftreg");
        $dumpvars;
        sin=0;load=0;shift=0;in=4'b0000;reset=1;#10;reset=0;#5;in=4'b1000;
        load=1;#30;
        load=0; shift=1;#100;
        load=1;shift=0;#20;load=0;shift=1;#200;load=1;#200;
        $finish;
    end
endmodule
